ECT114 Week 2 Homework

ECT114 Week 2 Homework
 

  1. Develop the logic symbol for logic gates showing two or more inputs.
  2. Identify the following logic gates by writing the name of the logic gate in the space provided. (5 Points)
  SYMBOL OF LOGIC GATE NAME OF LOGIC GATE
Ex. 2-input XNOR gate
a.  
_______________________________
b.  
_______________________________
c.  
_______________________________
d.  
_______________________________
e.  
_______________________________

 

  1. Generate the Boolean expression for the output of the logic gates using two or more input variables.
  2. Using the CPLD software, open a new Block Diagram/Schematic file. Draw the logic gate symbol for the following Boolean expressions. Connect and label input and output pins. Generate a schematic printout. (2 Points)
  3. X = A + B + C
  4. Y = A Å B

 
 
 

  1. For each logic gate write a corresponding Boolean expression in the space provided. (4 Points)

SYMBOL OF LOGIC GATE BOOLEAN EXPRESSION VHDL STATEMENT
Ex. Z = A·B Z <= A AND B;
a.  
_______________________________
 
_______________________________
b.  
_______________________________
 
_______________________________
c.  
_______________________________
 
_______________________________

 

  1. Create a truth table and timing diagram showing all possible input states for two or more input gates.
  2. Given the logic gate symbol, generate the corresponding truth table. (4 Points)
a. Input B
(H or L)
Input A
(H or L)
Lamp
(ON or OFF)
___ ___ _______
___ ___ _______
___ ___ _______
___ ___ _______

 
 
 
 
 
 

b.
 
Input B
(H or L)
Input A
(H or L)
Lamp
(ON or OFF)
___ ___ _______
___ ___ _______
___ ___ _______
___ ___ _______

 

  1. Given the following Boolean expressions, generate the corresponding truth tables. ( Points)

a.

  1. Observe the following waveforms. (4 Points)

 

  1. Which output waveform would be produced if INPUT1 and INPUT2 were the inputs to an AND gate? Is it waveform A, B, C, D, or E? Answer: ____
  2. Which output waveform would be produced if INPUT1 and INPUT2 were the inputs to an XOR gate? Is it waveform A, B, C, D, or E? Answer: ____

 
 
 
 

  1. Observe the following waveforms for inputs A, B, and C. (4 Points)
  2. If A and B were the input signals to a gate, draw the timing diagram of the output W.

 

  1. If A, B, and C were the input signals to a gate, draw the timing diagram of the output X.

 

  1. Given the following truth tables, draw the corresponding logic gate symbol, determine its Boolean expression, and write the VHDL assignment statement. (6 Points)

 

a.
Input B Input A Output X
ON ON OFF
OFF ON ON
ON OFF ON
OFF OFF OFF
Symbol:
 
 
Output X = ____________
VHDL: X <= ____________

 

b.
Input D1 Input D0 Output X
0 0 0
0 1 1
1 0 1
1 1 1
Symbol:
 
 
Output X = ____________
VHDL: X <= ____________

 

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